禄 xdevcfg_hw.h
xdevcfg_hw.h ( File view )
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******************************************************************************/
/****************************************************************************/
* @file xdevcfg_hw.h
* This file contains the hardware interface to the Device Config Interface.
* MODIFICATION HISTORY:
* ----- --- -------- ---------------------------------------------
* 1.00a hvm 02/07/11 First release
* 2.01a nm
08/01/12 Added defines for the PS Version bits,
removed the FIFO Flush bits from the
Miscellaneous Control Reg
* 2.03a nm
04/19/13 Fixed CR# 703728.
Updated the register definitions as per the latest TRM
version UG585 (v1.4) November 16, 2012.
* 2.04a kpc 10/07/13 Added function prototype.
* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
******************************************************************************/
#ifndef XDCFG_HW_H
/* prevent circular inclusions */
#define XDCFG_HW_H
/* by using protection macros */
#ifdef __cplusplus
extern &C& {
/***************************** Include Files *********************************/
#include &xil_types.h&
#include &xil_io.h&
/************************** Constant Definitions *****************************/
/** @name Register Map
* Offsets of registers from the start of the device
#define XDCFG_CTRL_OFFSET
0x00 /**& Control Register */
#define XDCFG_LOCK_OFFSET
0x04 /**& Lock Register */
#define XDCFG_CFG_OFFSET
0x08 /**& Configuration Register */
#define XDCFG_INT_STS_OFFSET
0x0C /**& Interrupt Status Register */
#define XDCFG_INT_MASK_OFFSET
0x10 /**& Interrupt Mask Register */
#define XDCFG_STATUS_OFFSET
0x14 /**& Status Register */
#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**& DMA Source Address Register */
#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**& DMA Destination Address Reg */
#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**& DMA Source Transfer Length */
#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**& DMA Destination Transfer */
#define XDCFG_ROM_SHADOW_OFFSET
0x28 /**& DMA ROM Shadow Register */
#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**& Multi BootAddress Pointer */
#define XDCFG_SW_ID_OFFSET
0x30 /**& Software ID Register */
#define XDCFG_UNLOCK_OFFSET
0x34 /**& Unlock Register */
#define XDCFG_MCTRL_OFFSET
0x80 /**& Miscellaneous Control Reg */
/** @name Control Register Bit definitions
#define XDCFG_CTRL_FORCE_RST_MASK 0x /**& Force
* Secure Reset
#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x /**& Program signal to
Reset FPGA
#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x /**& Control PL POR timer */
#define XDCFG_CTRL_PCAP_PR_MASK
0x /**& Enable PCAP for PR */
#define XDCFG_CTRL_PCAP_MODE_MASK 0x /**& Enable PCAP */
#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x /**& Enable PCAP send data
to FPGA every 4 PCAP
#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x /**& Multiboot Enable */
#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x /**& JTAG Chain Disable */
#define XDCFG_CTRL_USER_MODE_MASK 0x /**& User Mode Mask */
#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x /**& AES key source */
#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**& AES Enable Mask */
#define XDCFG_CTRL_SEU_EN_MASK
0x /**& SEU Enable Mask */
#define XDCFG_CTRL_SEC_EN_MASK
0x /**& Secure/Non Secure
Status mask
#define XDCFG_CTRL_SPNIDEN_MASK
0x /**& Secure Non Invasive
Debug Enable
#define XDCFG_CTRL_SPIDEN_MASK
0x /**& Secure Invasive
Debug Enable
#define XDCFG_CTRL_NIDEN_MASK
0x /**& Non-Invasive Debug
#define XDCFG_CTRL_DBGEN_MASK
0x /**& Invasive Debug
#define XDCFG_CTRL_DAP_EN_MASK
0x /**& DAP Enable Mask */
/** @name Lock register bit definitions
#define XDCFG_LOCK_AES_EFUSE_MASK 0x /**& Lock AES Efuse bit */
#define XDCFG_LOCK_AES_EN_MASK
0x /**& Lock AES_EN update */
#define XDCFG_LOCK_SEU_MASK
0x /**& Lock SEU_En update */
#define XDCFG_LOCK_SEC_MASK
0x /**& Lock SEC_EN and
#define XDCFG_LOCK_DBG_MASK
0x /**& This bit locks
security config
including: DAP_En,
NIDEN, SPNIEN
/** @name Config Register Bit definitions
#define XDCFG_CFG_RFIFO_TH_MASK
0x00000C00 /**& Read FIFO
Threshold Mask
#define XDCFG_CFG_WFIFO_TH_MASK
0x /**& Write FIFO Threshold
#define XDCFG_CFG_RCLK_EDGE_MASK 0x /**& Read data active
clock edge
#define XDCFG_CFG_WCLK_EDGE_MASK 0x /**& Write data active
clock edge
#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x /**& Disable Source address
increment mask
#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x /**& Disable Destination
address increment
/** @name Interrupt Status/Mask Register Bit definitions
#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x /**& Tri-state IO during
#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x /**& First configuration
#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x /**& Global power down */
#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x /**& Tri-state IO during
configuration
#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x /**& PL configuration
#define XDCFG_IXR_AXI_WTO_MASK
0x /**& AXI Write Address
or Data or response
#define XDCFG_IXR_AXI_WERR_MASK
0x /**& AXI Write response
#define XDCFG_IXR_AXI_RTO_MASK
0x /**& AXI Read Address or
response timeout
#define XDCFG_IXR_AXI_RERR_MASK
0x /**& AXI Read response
#define XDCFG_IXR_RX_FIFO_OV_MASK 0x /**& Rx FIFO Overflow */
#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x /**& Tx FIFO less than
threshold */
#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x /**& Rx FIFO greater than
threshold */
#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x /**& Illegal DMA command */
#define XDCFG_IXR_DMA_Q_OV_MASK
0x /**& DMA command queue
#define XDCFG_IXR_DMA_DONE_MASK
0x /**& DMA Command Done */
#define XDCFG_IXR_D_P_DONE_MASK
0x /**& DMA and PCAP
transfers Done
#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x /**& PCAP to DMA transfer
length error
#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x /**& HMAC error mask */
#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x /**& SEU Error mask */
#define XDCFG_IXR_PCFG_POR_B_MASK 0x /**& FPGA POR mask */
#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x /**& FPGA Reset mask */
#define XDCFG_IXR_PCFG_DONE_MASK 0x /**& Done Signal
#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x /**& Detect Positive edge
of Init Signal
#define XDCFG_IXR_PCFG_INIT_NE_MASK
0x /**& Detect Negative edge
of Init Signal
#define XDCFG_IXR_ERROR_FLAGS_MASK
(XDCFG_IXR_AXI_WTO_MASK | \
XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK |
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK |
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMA
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