暂无图片24bit 分辨率为 864*480 TFT LCD 驱动芯片型&&号：SSD1963大&&小：996.06KB
共0页厂&&商：FairchildSemiconductor主&&页：功能介绍：24bit 分辨率为 864*480 TFT LCD 驱动芯片推荐单价：无报价大小：996.06KB所需：2更多5已有1人评价浏览：8079次贡献者：yishuihan111贡献时间：日文档关键词相关推荐0页热门文档2页3页237页28页2页您最近浏览过的文档产业技术特色栏目社群供应链服务媒体服务版权所有 (C) 深圳华强聚丰电子科技有限公司SSD1963_伤城文章网
SOLOMON SYSTECHSEMICONDUCTOR TECHNICAL DATASSD1963Advance Information1215KB Embedded Display SRAM LCD Display ControllerThis document contains information on a new product. Specifications and information herein are subject to change without notice. http://www. SSD1963 Rev 1.2 P 1/94 Copyright ? 2010 Solomon Systech LimitedMay 2010Appendix: IC Revision history of SSD1963 Specification Version 0.10 21-Nov-08 0.10 08-Dec-08 Change Items 1st Release 1. 2. 3. 4. Changed the set_pll_mnk to set_pll_mn in section 7.2 Change register name in section 8 Removed ABC Revised description for REG 0x00, 0x01, 0x0C, 0x0D, 0x0E, 0x10, 0x11, 0x21, 0x26, 0x28, 0x2A, 0x2B, 0x2C, 0x2E, 0x33, 0x34, 0x35, 0x36, 0x37, 0x3A, 0x3C, 0x3E, 0x44, 0x45, 0xA1, 0xB0, 0xB1, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBE, 0xBF, 0xD0, 0xD1, 0xD4, 0xE5. 5. Added max VIH in Table 12-1 6. Added Table 9-1 7. Added Table 11-1 8. Revised Figure 9-19 9. Revised Figure 14-2 10. Revised Figure 13-5 11. Corrected typo for Table 7-2 12. Revised test condition for 12 and 13 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 1. 2. Changed status to Advance Information Update min/max rating of VDDD and VDDPLL in Table 11-1 Added tape and reel drawing of 128-pin LQFP package in Section 15.3 Revised Section 13.2 5. Added 12 bits for Table 7-1 Removed TTL interface Revised section 7.1.5 Change the title of section 7.2 Revised command description in section 8 Removed the command 0x0C and 0x3A Added figures in section 13.4 Revised figures in section 13.3 Revise Table 6-1 Update Table 7-1 Revised section 9.72 Effective Date 24-Nov-08 10-Dec-081.0 07-May-0918-May-091.1 23-Dec-09 1.2 31-May-1018-Jan-101. Add Table 13-715-Jul-10Solomon SystechMay 2010P 2/94Rev 1.2SSD1963CONTENTS 1 2 3 4 5 GENERAL DESCRIPTION ....................................................................................................... 8 FEATURES................................................................................................................................... 8 ORDERING INFORMATION ................................................................................................... 8 BLOCK DIAGRAM .................................................................................................................... 9 PIN ARRANGEMENT.............................................................................................................. 105.1 5.2 80 BALLS TFBGA................................................................................................................................................10 128 PINS LQFP ....................................................................................................................................................116 7PIN DESCRIPTIONS ................................................................................................................ 13 FUNCTIONAL BLOCK DESCRIPTIONS ............................................................................ 167.1 MCU INTERFACE .................................................................................................................................................16 7.1.1 6800 Mode ..................................................................................................................................................16 7.1.2 8080 Mode ..................................................................................................................................................16 7.1.3 Register Pin Mapping .................................................................................................................................16 7.1.4 Pixel Data Format ......................................................................................................................................16 7.1.5 Tearing Effect Signal (TE) ..........................................................................................................................17 7.2 SYSTEM CLOCK GENERATION .............................................................................................................................18 7.3 FRAME BUFFER....................................................................................................................................................19 7.4 SYSTEM CLOCK AND RESET MANAGER ...............................................................................................................19 7.5 LCD CONTROLLER ..............................................................................................................................................20 7.5.1 Display Format ...........................................................................................................................................20 7.5.2 General Purpose Input/Output (GPIO) ......................................................................................................208 9COMMAND TABLE ................................................................................................................. 21 COMMAND DESCRIPTIONS................................................................................................. 249.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24NOP ......................................................................................................................................................................24 SOFT_RESET .........................................................................................................................................................24 GET_POWER_MODE ..............................................................................................................................................24 GET_ADDRESS_MODE ..........................................................................................................................................25 GET_DISPLAY_MODE ...........................................................................................................................................25 GET_TEAR_EFFECT_STATUS ................................................................................................................................26 ENTER_SLEEP_MODE ...........................................................................................................................................27 EXIT_SLEEP_MODE ..............................................................................................................................................27 ENTER_PARTIAL_MODE .......................................................................................................................................27 ENTER_NORMAL_MODE .......................................................................................................................................27 EXIT_INVERT_MODE ............................................................................................................................................28 ENTER_INVERT_MODE .........................................................................................................................................28 SET_GAMMA_CURVE ...........................................................................................................................................29 SET_DISPLAY_OFF ...............................................................................................................................................29 SET_DISPLAY_ON .................................................................................................................................................29 SET_COLUMN_ADDRESS ......................................................................................................................................30 SET_PAGE_ADDRESS ............................................................................................................................................30 WRITE_MEMORY_START ......................................................................................................................................31 READ_MEMORY_START .......................................................................................................................................32 SET_PARTIAL_AREA.............................................................................................................................................32 SET_SCROLL_AREA ..............................................................................................................................................34 SET_TEAR_OFF.....................................................................................................................................................36 SET_TEAR_ON ......................................................................................................................................................36 SET_ADDRESS_MODE ...........................................................................................................................................36SSD1963Rev 1.2P 3/94May 2010Solomon Systech9.25 9.26 9.27 9.28 9.29 9.30 9.31 9.32 9.33 9.34 9.35 9.36 9.37 9.38 9.39 9.40 9.41 9.42 9.43 9.44 9.45 9.46 9.47 9.48 9.49 9.50 9.51 9.52 9.53 9.54 9.55 9.56 9.57 9.58 9.59 9.60 9.61 9.62 9.63 9.64 9.65 9.66 9.67 9.68 9.69 9.70 9.71 9.72 9.73 9.74 9.75SET_SCROLL_START ............................................................................................................................................39 EXIT_IDLE_MODE ................................................................................................................................................40 ENTER_IDLE_MODE .............................................................................................................................................40 WRITE_MEMORY_CONTINUE ................................................................................................................................41 READ_MEMORY_CONTINUE .................................................................................................................................42 SET_TEAR_SCANLINE ...........................................................................................................................................43 GET_SCANLINE ....................................................................................................................................................43 READ_DDB ...........................................................................................................................................................44 SET_LCD_MODE ...................................................................................................................................................44 GET_LCD_MODE ..................................................................................................................................................46 SET_HORI_PERIOD ...............................................................................................................................................47 GET_HORI_PERIOD ...............................................................................................................................................48 SET_VERT_PERIOD ...............................................................................................................................................49 GET_VERT_PERIOD ..............................................................................................................................................49 SET_GPIO_CONF ...................................................................................................................................................50 GET_GPIO_CONF ..................................................................................................................................................51 SET_GPIO_VALUE ................................................................................................................................................52 GET_GPIO_STATUS ...............................................................................................................................................52 SET_POST_PROC...................................................................................................................................................53 GET_POST_PROC ..................................................................................................................................................53 SET_PWM_CONF...................................................................................................................................................54 GET_PWM_CONF ..................................................................................................................................................55 SET_LCD_GEN0....................................................................................................................................................57 GET_LCD_GEN0 ...................................................................................................................................................58 SET_LCD_GEN1....................................................................................................................................................59 GET_LCD_GEN1 ...................................................................................................................................................60 SET_LCD_GEN2....................................................................................................................................................61 GET_LCD_GEN2 ...................................................................................................................................................62 SET_LCD_GEN3....................................................................................................................................................63 GET_LCD_GEN3 ...................................................................................................................................................64 SET_GPIO0_ROP ...................................................................................................................................................65 GET_GPIO0_ROP...................................................................................................................................................65 SET_GPIO1_ROP ...................................................................................................................................................66 GET_GPIO1_ROP...................................................................................................................................................67 SET_GPIO2_ROP ...................................................................................................................................................67 GET_GPIO2_ROP...................................................................................................................................................68 SET_GPIO3_ROP ...................................................................................................................................................69 GET_GPIO3_ROP...................................................................................................................................................69 SET_DBC_CONF....................................................................................................................................................70 GET_DBC_CONF ...................................................................................................................................................71 SET_DBC_TH ........................................................................................................................................................72 GET_DBC_TH .......................................................................................................................................................73 SET_PLL ...............................................................................................................................................................73 SET_PLL_MN ........................................................................................................................................................74 GET_PLL_MN .......................................................................................................................................................75 GET_PLL_STATUS ................................................................................................................................................75 SET_DEEP_SLEEP .................................................................................................................................................75 SET_LSHIFT_FREQ ................................................................................................................................................76 GET_LSHIFT_FREQ ...............................................................................................................................................76 SET_PIXEL_DATA_INTERFACE .............................................................................................................................78 GET_PIXEL_DATA_INTERFACE .............................................................................................................................7810 1111.1MAXIMUM RATINGS.......................................................................................................... 79 RECOMMENDED OPERATING CONDITIONS ............................................................. 79POWER-UP SEQUENCE ..........................................................................................................................................7912 13DC CHARACTERISTICS..................................................................................................... 80 AC CHARACTERISTICS..................................................................................................... 80May 2010 P 4/94 Rev 1.2 SSD1963Solomon Systech13.1 CLOCK TIMING ....................................................................................................................................................80 13.2 MCU INTERFACE TIMING ....................................................................................................................................81 13.2.1 Parallel 6800-series Interface Timing ........................................................................................................81 13.2.2 Parallel 8080-series Interface Timing ........................................................................................................83 13.3 PARALLEL LCD INTERFACE TIMING....................................................................................................................85 13.4 SERIAL RGB INTERFACE TIMING ........................................................................................................................8614 1515.1 15.2 15.3APPLICATION EXAMPLE.................................................................................................. 89 PACKAGE INFORMATION................................................................................................ 91PACKAGE MECHANICAL DRAWING FOR 80 BALLS TFBGA .................................................................................91 PACKAGE MECHANICAL DRAWING FOR 128 PINS LQFP......................................................................................92 TAPE & REEL DRAWING FOR 128 PINS LQFP ......................................................................................................93SSD1963Rev 1.2P 5/94May 2010Solomon SystechTABLESTABLE 3-1: ORDERING INFORMATION ...................................................................................................................................8 TABLE 5-1: TFBGA PIN ASSIGNMENT TABLE .....................................................................................................................10 TABLE 5-2 : LQFP PIN ASSIGNMENT TABLE .......................................................................................................................12 TABLE 6-1: MCU INTERFACE PIN MAPPING ........................................................................................................................13 TABLE 6-2: LCD INTERFACE PIN MAPPING .........................................................................................................................14 TABLE 6-3: CONTROL SIGNAL PIN MAPPING .......................................................................................................................14 TABLE 6-4: POWER PIN MAPPING ........................................................................................................................................14 TABLE 6-5 : LCD INTERFACE PIN MAPPING ........................................................................................................................15 TABLE 7-1: PIXEL DATA FORMAT .......................................................................................................................................17 TABLE 7-2: FRAME BUFFER SETTINGS REGARDING TO SET_ADDRESS_MODE COMMAND 0X36 ...........................................19 TABLE 9-1 ENTER IDLE MODE MEMORY CONTENT VS DISPLAY COLOR ...............................................................................41 TABLE 10-1: MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS) ...................................................................................79 TABLE 11-1: RECOMMENDED OPERATING CONDITION ........................................................................................................79 TABLE 12-1 : DC CHARACTERISTICS ...................................................................................................................................80 TABLE 13-1: CLOCK INPUT REQUIREMENTS FOR CLK (PLL-BYPASS) ................................................................................80 TABLE 13-2 : CLOCK INPUT REQUIREMENTS FOR CLK .......................................................................................................80 TABLE 13-3 : CLOCK INPUT REQUIREMENTS FOR CRYSTAL OSCILLATOR XTAL .................................................................80 TABLE 13-4: PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (USE CS# AS CLOCK)...................................81 TABLE 13-5: PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (USE E AS CLOCK) .......................................82 TABLE 13-6: PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS .....................................................................83 TABLE 13-7: QUICK REFERENCE TABLE FOR LCD PARAMETER SETTING .............................................................................88Solomon SystechMay 2010P 6/94Rev 1.2SSD1963FIGURESFIGURE 4-1: SSD1963 BLOCK DIAGRAM ..............................................................................................................................9 FIGURE 5-1: PINOUT DIAGRAM CTFBGA (TOPVIEW).........................................................................................................10 FIGURE 5-2 : PINOUT DIAGRAM C LQFP (TOPVIEW) ...........................................................................................................11 FIGURE 7-1: RELATIONSHIP BETWEEN TEARING EFFECT SIGNAL AND MCU MEMORY WRITING........................................18 FIGURE 7-2: CLOCK CONTROL DIAGRAM ............................................................................................................................19 FIGURE 7-3: STATE DIAGRAM OF SSD1963.........................................................................................................................20 FIGURE 9-1: EXIT INVERT MODE EXAMPLE ..........................................................................................................................28 FIGURE 9-2: ENTER INVERT MODE EXAMPLE .......................................................................................................................29 FIGURE 9-3: SET COLUMN ADDRESS EXAMPLE ...................................................................................................................30 FIGURE 9-4: SET PAGE ADDRESS EXAMPLE .........................................................................................................................31 FIGURE 9-5: SET PARTIAL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 0 WHEN END ROW & START ROW ..................33 FIGURE 9-6: SET PARTIAL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 1 WHEN END ROW & START ROW ..................33 FIGURE 9-7: SET PARTIAL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 0 WHEN START ROW & END ROW ..................33 FIGURE 9-8: SET PARTIAL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 1 WHEN START ROW & END ROW ..................33 FIGURE 9-9: SET SCROLL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 0.....................................................................35 FIGURE 9-10: SET SCROLL AREA WITH SET_ADDRESS_MODE (0X36) A[4] = 1....................................................................35 FIGURE 9-11: A[7] PAGE ADDRESS ORDER .........................................................................................................................37 FIGURE 9-12: A[6] COLUMN ADDRESS ORDER ....................................................................................................................37 FIGURE 9-13: A[5] PAGE / COLUMN ADDRESS ORDER ........................................................................................................37 FIGURE 9-14: A[3] RGB ORDER..........................................................................................................................................38 FIGURE 9-15: A[1] FLIP HORIZONTAL .................................................................................................................................38 FIGURE 9-16: A[0] FLIP VERTICAL ......................................................................................................................................39 FIGURE 9-17: SET SCROLL START WITH SET_ADDRESS_MODE (0X36) A[4] = 0 ..................................................................39 FIGURE 9-18: SET SCROLL START WITH SET_ADDRESS_MODE (0X36) A[4] = 1 ..................................................................40 FIGURE 9-19: PWM SIGNAL ................................................................................................................................................54 FIGURE 11-1: POWER-UP SEQUENCE ...................................................................................................................................79 FIGURE 13-1: PARALLEL 6800-SERIES INTERFACE TIMING DIAGRAM (USE CS# AS CLOCK)...............................................81 FIGURE 13-2: PARALLEL 6800-SERIES INTERFACE TIMING DIAGRAM (USE E AS CLOCK) ...................................................82 FIGURE 13-3: PARALLEL 8080-SERIES INTERFACE TIMING DIAGRAM (WRITE CYCLE) .......................................................83 FIGURE 13-4: PARALLEL 8080-SERIES INTERFACE TIMING DIAGRAM (READ CYCLE).........................................................84 FIGURE 13-5: GENERIC TFT PANEL TIMING ........................................................................................................................85 FIGURE 13-6: SERIAL RGB INTERFACE TIMING (WITHOUT DUMMY MODE).........................................................................86 FIGURE 13-7: SERIAL RGB INTERFACE TIMING (WITH DUMMY MODE) ...............................................................................87 FIGURE 14-1 : APPLICATION CIRCUIT FOR SSD1963 (WITH DIRECT CLOCK INPUT).............................................................89 FIGURE 14-2 : APPLICATION CIRCUIT FOR SSD1963 (WITH CRYSTAL OSCILLATOR INPUT) .................................................90SSD1963Rev 1.2P 7/94May 2010Solomon Systech1GENERAL DESCRIPTIONSSD1963 is a display controller of 1215K byte frame buffer to support up to 864 x 480 x 24bit graphics content. It also equips parallel MCU interfaces in different bus width to receive graphics data and command from MCU. Its display interface supports common RAM-less LCD driver of color depth up to 24 bit-perpixel.2FEATURES? Display feature ? Built-in 1215K bytes frame buffer. Support up to 864 x 480 at 24bpp display ? Support TFT 18/24-bit generic RGB interface panel ? Support 8-bit serial RGB interface ? Hardware rotation of 0, 90, 180, 270 degree ? Hardware display mirroring ? Hardware windowing ? Programmable brightness, contrast and saturation control ? Dynamic Backlight Control (DBC) via PWM signal MCU connectivity ? 8/9/16/18/24-bit MCU interface ? Tearing effect signal I/O Connectivity ? 4 GPIO pins Built-in clock generator Deep sleep mode for power saving Core supply power (VDDPLL and VDDD): 1.2V±0.1V I/O supply power(VDDIO): 1.65V to 3.6V LCD interface supply power (VDDLCD): 1.65V to 3.6V? ? ? ? ? ??3ORDERING INFORMATIONTable 3-1: Ordering Information Ordering Part Number SSD1963G41 SSD1963QL9 SSD1963QL9R Package Form TFBGA-80 (Tray) LQFP-128 (Tray) LQFP-128 (Tape & Reel)Solomon SystechMay 2010P 8/94Rev 1.2SSD19634BLOCK DIAGRAMFigure 4-1: SSD1963 Block Diagram`SSD1963Rev 1.2P 9/94May 2010Solomon Systech5 5.1PIN ARRANGEMENT 80 balls TFBGAFigure 5-1: Pinout Diagram CTFBGA (Topview)Table 5-1: TFBGA Pin Assignment TablePin # A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 Signal Name LDATA16 LDATA15 GAMAS1 TE LSHIFT GPIO2 GPIO1 GPIO0 VDDLCD LDATA14 LDATA13 GAMAS0 PWM LLINE GPIO3 LDATA20 XTAL_OUT Pin # C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 Signal Name VDDLCD LDATA12 LDATA11 LDATA10 LDATA9 LDEN LDATA17 LDATA21 XTAL_IN VSS LDATA8 LDATA7 LDATA6 LDATA5 LFRAME LDATA23 LDATA22 VSSPLL Pin # E1 E2 E3 E4 E5 E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 Signal Name LDATA4 LDATA3 LDATA2 LDATA1 VSS VDDD R/W# (WR#) D[4] VDDPLL LDATA18 LDATA19 LDATA0 D[19] VSS VDDD E(RD#) D[3] CLK Pin # G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 Signal Name D[22] D[23] D[18] D[13] D[10] D[7] D/C# D[2] D[1] D[21] D[17] D[15] D[12] D[9] D[6] CS# CONF D[0] Pin # J1 J2 J3 J4 J5 J6 J7 J8 J9 Signal Name D[20] D[16] D[14] D[11] D[8] D[5] RESET# VSS VDDIOSolomon SystechMay 2010P 10/94Rev 1.2SSD19635.2128 pins LQFPFigure 5-2 : Pinout Diagram C LQFP (Topview)R/W#(WR#)RESET#E(RD#)VDDIOVDDIOVDDIOVDDIO1281271261251241231221211201191181171161151141131121111101091081071061051041031021011009998VDDD VSS VSS VDDIO VSS VDDD D0 D1 D2 D3 D4 VDDIO VSS VDDD CLK VDDIO VSS VDDPLL VSSPLL VSS VDDD XTAL_IN VSS XTAL_OUT VDDD VSS VDDLCD LDATA23 LDATA22 LDATA21 LDATA20 VDDD97VDDIOCONFVDDDVDDDVDDDVDDDD/C#VSSVSSVSSVSSCS#D10D11D12D13D14D15D16D17D5D6D7D8D91 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 6496 95 94 93 92 91 90 89 88 87 86 85 84 83 82VSS VDDIO VSS VDDD D20 D21 D22 D23 D18 D19 LDATA18 LDATA19 VDDLCD VSS VDDD LDATA0 LDATA1 LDATA2 LDATA3 LDATA4 LDATA5 VDDLCD VSS VDDD LDATA6 LDATA7 LDATA8 LDATA9 LDATA10 LDATA11 VDDLCD VSSSSD196381 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65LDATA16LDATA15LDATA14LDATA13LDATA12VDDLCDLDATA17GAMAS0GAMAS1VDDLCDVDDLCDVDDLCDVDDLCDLFRAMEGPIO0GPIO1GPIO2GPIO3LSHIFTVDDDVDDDVDDDSSD1963VDDDLLINELDENPWMVSSVSSVSSVSSVSSTERev 1.2P 11/94May 2010Solomon SystechTable 5-2 : LQFP Pin Assignment Table Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Signal Name VDDD VSS VSS VDDIO VSS VDDD D0 D1 D2 D3 D4 VDDIO VSS VDDD CLK VDDIO VSS VDDPLL VSSPLL VSS VDDD XTAL_IN VSS XTAL_OUT VDDD VSS VDDLCD LDATA23 LDATA22 LDATA21 LDATA20 VDDD Pin # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Signal Name VSS VDDLCD LDATA17 GPIO0 GPIO1 GPIO2 GPIO3 VDDD VSS VDDLCD LFRAME LLINE LSHIFT VDDD VSS VDDLCD LDEN TE PWM GAMAS0 GAMAS1 VDDLCD VSS VDDD VSS VDDLCD LDATA16 LDATA15 LDATA14 LDATA13 LDATA12 VDDD Pin # 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Signal Name VSS VDDLCD LDATA11 LDATA10 LDATA9 LDATA8 LDATA7 LDATA6 VDDD VSS VDDLCD LDATA5 LDATA4 LDATA3 LDATA2 LDATA1 LDATA0 VDDD VSS VDDLCD LDATA19 LDATA18 D19 D18 D23 D22 D21 D20 VDDD VSS VDDIO VSS Pin # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Signal Name VDDIO D17 D16 VDDIO VSS VDDD D15 D14 D13 D12 D11 VDDIO VSS VDDD D10 D9 D8 D7 D6 D5 VDDIO VSS VDDD R/W#(WR#) E(RD#) D/C# CS# VDDIO VSS VDDD RESET# CONFSolomon SystechMay 2010P 12/94Rev 1.2SSD19636PIN DESCRIPTIONSI = Input O =Output IO = Bi-directional (input/output) P = Power pinHi-Z = High impedanceKey:Table 6-1: MCU Interface Pin Mapping Pin Name CLK XTAL_IN XTAL_OUT CS# D/C# E(RD#) Reference Type Voltage Level I I O I I I VDDIO VDDIO VDDIO VDDIO VDDIO TFBGA Pin # F9 C9 B9 H7 G7 F7 E7 E8, F4, F8, G1, G2, G3, G4, G5, G6, G8, G9, H1, H2, H3, H4, H5, H6, H9, J1, J2,J3, J4, J5, J6 A5 LQFP Pin # 15 22 24 123 122 121 120 Description TTL clock input. This pin should be tied to VSS if TTL clock input is not used Crystal oscillator input. This pin should be tied to VSS if not used Crystal oscillator output. This pin should be floating if not used Chip select Data/Command select 6800 mode: E (enable signal) 8080 mode: RD# (read strobe signal) 6800 mode: R/W# 0: Write cycle 1: Read cycle 8080 mode: WR# (write strobe signal)R/W#(WR#)ID[23:0]IOVDDIOTEOVDDLCD7, 8, 9, 10, 11, 87, 88, 89, 90, 91, 92, 98, 99, Data bus. Pins not used should be floating 103, 104, 105, 106, 107, 111, 112, 113, 114, 115, 116 50 Tearing effectSSD1963Rev 1.2P 13/94May 2010Solomon SystechTable 6-2: LCD Interface Pin Mapping Pin Name LFRAME LLINE LSHIFT LDEN Reference Type Voltage Level O VDDLCD O VDDLCD O VDDLCD O VDDLCD TFBGA Pin # D6 B6 A6 C6 A2, A3, B2, B3, B8, C2, C3, C4, C5, C7, C8, D2, D3, D4, D5, D7, D8, E1, E2, E3, E4, F1, F2, F3 A7, A8, A9, B7 A4, B4 B5 LQFP Pin # 43 44 45 49 28, 29, 30, 31, 35, 59, 60, 61, 62, 63, 67, 68, 69, 70, 71, 72, 76, 77, 78, 79, 80, 81, 85, 86 Description Vertical sync (Frame pulse) Horizontal sync (Line pulse) Pixel clock (Pixel shift signal) Data validLDATA[23:0]OVDDLCDRGB dataGPIO[3:0] GAMAS [1:0] PWMIO O OVDDLCD VDDLCD VDDLCDThese pins can be configured for display 36, 37, 38, 39 miscellaneous signals or as general purpose I/O. Default as input 52, 53 Gamma selection for panel 51 PWM output for backlight driverTable 6-3: Control Signal Pin Mapping Pin Name RESET# CONF Reference Type Voltage Level I VDDIO I VDDIO TFBGA Pin # J7 H8 LQFP Pin # 127 128 Description Master synchronize reset MCU interface configuration 0: 6800 Interface 1: 8080 InterfaceTable 6-4: Power Pin Mapping Pin Name VDDD VDDLCD VDDPLL VDDIO Type P P P P LQFP Description Pin # 1, 6, 14, 21, 25, 32, E6, F6 40, 46, 56, 64, 73, 82, Power supply for internal digital circuit 93, 102, 110, 119, 126 27, 34, 42, 48, 54, 58, B1, C1 Power supply for LCD interface related pads 66, 75, 84 Power supply for internal analog circuit and E9 18 analog I/O pads 4, 12, 16, J9 95, 97, 100, 108, 117, Power supply for digital I/O pads 124 2, 3, 5, 13, 17, 20, 23, 26, 33, 41, 47, 55, 57, D1, E5, F5, J8 Ground for internal digital circuit 65, 74, 83, 94, 96, 101, 109, 118, 125 Ground for internal analog circuit and analog I/O D9 19 pads TFBGA Pin #VSS VSSPLLP PSolomon SystechMay 2010P 14/94Rev 1.2SSD1963Table 6-5 : LCD Interface Pin Mapping Pin Names LFRAME LLINE LSHIFT LDEN LDATA23 LDATA22 LDATA21 LDATA20 LDATA19 LDATA18 LDATA17 LDATA16 LDATA15 LDATA14 LDATA13 LDATA12 LDATA11 LDATA10 LDATA9 LDATA8 LDATA7 LDATA6 LDATA5 LDATA4 LDATA3 LDATA2 LDATA1 LDATA0 24-bit 18-bit FRAME LINE SHIFT DEN Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 8-bit serialR7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 D7 D6 D5 D4 D3 D2 D1 D0Note (1) These pin mappings use signal names commonly used for each panel type, however signal names may differ between panel manufacturers.SSD1963Rev 1.2P 15/94May 2010Solomon Systech7 7.1FUNCTIONAL BLOCK DESCRIPTIONS MCU InterfaceThe MCU interface connects the MCU and SSD1963 graphics controller. The MCU interface can be configured as 6800 mode and 8080 mode by the CONF pin. By pulling the CONF pin to VSSIO, the MCU interface will be configured as 6800 mode interface. If the CONF pin is connected to VDDIO, the MCU interface will be configure in 8080 mode.7.1.16800 ModeThe 6800 mode MCU interface consist of CS#, D/C#, E, R/W#, D[23:0], and TE signals (Please refer to Table 6-1 for pin multiplexed with 8080 mode). This interface supports both fixed E and clock E scheme to define a read/write cycle. If the E signal is kept high and used as enable signal, the CS# signal acts as a bus clock, the data or command will be latched into the system at the rising edge of CS#. If the user wants to use the E pin as the clock pin, the CS# pin then need to be fixed to logic 0 to select the chip. Then the falling edge of the E signal will latch the data or command. For details, please refer to the timing diagram in chapter 13.2.1.7.1.28080 ModeThe 8080 mode MCU interface consist of CS#, D/C#, RD#, WR#, D[23:0] and TE signals (Please refer to Table 6-1 for pin multiplexed with 6800 mode). This interface use WR# to define a write cycle and RD# for read cycle. If the WR# goes low when the CS# signal is low, the data or command will be latched into the system at the rising edge of WR#. Similarly, the read cycle will start when RD# goes low and end at the rising edge of RD#. The detailed timing will show in the chapter 13.2.2.7.1.3Register Pin MappingWhen user access the registers via the parallel MCU interface, only D[7:0] will be used regardless the width of the pixel data is. Therefore, D[23:8] will only be used to address the display data only. This provided the possibility that the pixel data format as shown in Table 7-1 can be configured by command 0xF0.7.1.4Pixel Data FormatBoth 6800 and 8080 support 8-bit, 9-bit, 16-bit, 18-bit and 24-bit data bus. Depending on the width of the data bus, the display data are packed into the data bus in different ways.Solomon SystechMay 2010P 16/94Rev 1.2SSD1963Table 7-1: Pixel Data FormatInterface 24 bits 18 bits 16 bits (565 format)Cycle D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 1 1 1 1st st st stR7R6R5R4R3R2R1 R5R0 R4G7 R3 R5 R7 B7 G7G6 R2 R4 R6 B6 G6G5 R1 R3 R5 B5 G5G4 R0 R2 R4 B4 G4G3 G5 R1 R3 B3 G3 R7 G3G2 G4 G5 R2 B2 G2 R6 G2G1 G3 G4 R1 B1 G1 R5 G1G0 G2 G3 R0 B0 G0 R4 G0 R5 G2B7 G1 G2 G7 R7 B7 R3 B7 R4 G1 R7 G7 B7B6 G0 G1 G6 R6 B6 R2 B6 R3 G0 R6 G6 B6B5 B5 G0 G5 R5 B5 R1 B5 R2 B5 R5 G5 B5B4 B4 B5 G4 R4 B4 R0 B4 R1 B4 R4 G4 B4B3 B3 B4 G3 R3 B3 G7 B3 R0 B3 R3 G3 B3B2 B2 B3 G2 R2 B2 G6 B2 G5 B2 R2 G2 B2B1 B1 B2 G1 R1 B1 G5 B1 G4 B1 R1 G1 B1B0 B0 B1 G0 R0 B0 G4 B0 G3 B0 R0 G0 B016 bits2 3nd rd12 bits1s t 2nd1 2st nd st9 bits1 8 bits 2 3nd rd7.1.5Tearing Effect Signal (TE)The Tearing Effect Signal (TE) is a feedback signal from the LCD Controller to MCU. This signal reveals the display status of LCD controller. In the non-display period, the TE signal will go high. Therefore, this signal enables the MCU to send data by observing the non-display period to avoid tearing. Figure 7-1 shows how the TE signal helps to avoid tearing. If the MCU writing speed is slower than the display speed, the display data should be updated after the LCD controller start to scan the frame buffer. Then the LCD controller will always display the old memory content until the next frame. However, if the MCU is faster than the LCD controller, it should start updating the display content in the vertical non-display period (VNDP) to enable the LCD controller will always get the newly updated data.SSD1963Rev 1.2P 17/94May 2010Solomon SystechFigure 7-1: Relationship between Tearing Effect Signal and MCU Memory WritingIn SSD1963, users can configure the TE signal to reflect the vertical non-display period only or reflect both vertical and horizontal non-display period. With the additional horizontal non-display period information, the MCU can control the refresh action in more accurately by counting the horizontal line scanned by the LCD controller. Usually, a fast MCU will not need horizontal non-display period. But a slow MCU will need it to ensure the frame buffer update process always lags behind the LCD controller.7.2System Clock GenerationThe system clock of SSD1963 is generated by the built-in PLL. The reference clock of the PLL can come from either the CLK pin or the external crystal oscillator. Since the CLK pin and the output of the oscillator was connected to PLL with an “OR” gate, the unused clock must be tied to VSS. Before the PLL output is configured as the system clock by the bit 1 of “set_pll” command 0xE0, the system will be clocked by the reference clock. This enables the user to send the “set_pll_mn” command 0xE2 to the PLL for frequency configuration. When the PLL frequency is configured and the PLL was enabled with the bit 0 of “set_pll” command 0xE0, the user should still wait for 100ms for the PLL to lock. Then the PLL is ready and can be configured as system clock with the bit 1 of “set_pll” command 0xE0.Solomon SystechMay 2010P 18/94Rev 1.2SSD1963Figure 7-2: Clock Control Diagramset_pll bit 1 set_pll bit 0CLKEN REF FBPLL1/M1 System Clock 0OSCXTAL_IN XTAL_OUT1/NEXTERNAL CRYSTAL7.3Frame BufferThere are 1215K bytes built-in SRAM inside SSD1963 to use as frame buffer. When the frame buffer is written or read, the “address counter” will automatically increase by one or decrease by one depends on the frame buffer settings.Table 7-2: Frame Buffer Settings regarding to set_address_mode command 0x367.4System Clock and Reset ManagerThe “System Clock and Reset Manager” distributes the reset signal and clock signal to the entire system. It controls the Clock Generator and contains clock gating circuitry to turn on and off the clock of each functional module. Also, it divides the root clock from Clock Generator to operation clocks for different module. The System Clock and Reset Manager also manage the reset signals to ensure all the module are reset to appropriate status when the system are in reset state, deep sleep state, sleep state and display state. Figure 7-3 shows a state diagram of four operation states of SSD1963.SSD1963Rev 1.2P 19/94May 2010Solomon SystechFigure 7-3: State Diagram of SSD19637.5 7.5.1LCD Controller Display FormatThe LCD controller reads the frame buffer and generates display signals according to the selected display panel format. SSD1963 supports common RAM-less TFT driver using generic RGB data format.7.5.2General Purpose Input/Output (GPIO)The GPIO pins can operate in 2 modes, GPIO mode and miscellaneous display signal mode. When the pins are configured as GPIOs, these pins can be controlled directly by MCU. Therefore, user can use these pins to emulate other interface such as SPI or I2C. If these pins are configured as display signals, they will toggle with display periodically according to the signal settings. They can be set to toggle once a frame, once a line or in arbitrary period. Therefore they can be configured as some common signal needed for different panels such as STH or LP.Solomon SystechMay 2010P 20/94Rev 1.2SSD19638COMMAND TABLEHex Code 0x00 0x01 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 Command nop soft_reset get_power_mode get_address_mode Reserved get_display_mode get_tear_effect_status Reserved enter_sleep_mode Description No operation Software Reset Get the current power mode Get the frame buffer to the display panel read order Reserved The SSD1963 returns the Display Image Mode. Get the Tear Effect status Reserved Turn off the panel. This command will pull low the GPIO0. If GPIO0 is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf, this command will be ignored. Turn on the panel. This command will pull high the GPIO0. If GPIO0 is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf, this command will be ignored. Part of the display area is used for image display. The whole display area is used for image display. Displayed image colors are not inverted. Displayed image colors are inverted. Selects the gamma curve used by the display panel. Blanks the display panel Show the image on the display panel Set the column address Set the page address Transfer image information from the host processor interface to the SSD1963 starting at the location provided by set_column_address and set_page_address Transfer image data from the SSD1963 to the host processor interface starting at the location provided by set_column_address and set_page_address Defines the partial display area on the display panel Defines the vertical scrolling and fixed area on display area Synchronization information is not sent from the SSD1963 to the host processor Synchronization information is sent from the SSD1963 to the host processor at the start of VFP Set the read order from frame buffer to the display panel Defines the vertical scrolling starting point Full color depth is used for the display panel Reduce color depth is used on the display panel. Reserved Transfer image information from the host processor interface to the SSD1963 from the last written location Read image data from the SSD1963 continuing after the last read_memory_continue or read_memory_start0x11 0x12 0x13 0x20 0x21 0x26 0x28 0x29 0x2A 0x2B 0x2Cexit_sleep_mode enter_partial_mode enter_normal_mode exit_invert_mode enter_invert_mode set_gamma_curve set_display_off set_display_on set_column_address set_page_address write_memory_start0x2E 0x30 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3C 0x3Eread_memory_start set_partial_area set_scroll_area set_tear_off set_tear_on set_address_mode set_scroll_start exit_idle_mode enter_idle_mode Reserved write_memory_continue read_memory_continueSSD1963Rev 1.2P 21/94May 2010Solomon SystechHex Code 0x44 0x45 0xA1 0xA8 0xB0 0xB1 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCCCommand set_tear_scanline get_scanline read_ddb Reserved set_lcd_mode_ get_lcd_mode set_hori_period get_hori_period set_vert_period get_vert_period set_gpio_conf get_gpio_conf set_gpio_value get_gpio_status set_post_proc get_post_proc set_pwm_conf get_pwm_conf set_lcd_gen0 get_lcd_gen0 set_lcd_gen1 get_lcd_gen1 set_lcd_gen2 get_lcd_gen2 set_lcd_gen3 get_lcd_gen3 set_gpio0_rop get_gpio0_rop set_gpio1_rop get_gpio1_rop set_gpio2_ropDescription Synchronization information is sent from the SSD1963 to the host processor when the display panel refresh reaches the provided scanline Get the current scan line Read the DDB from the provided location Reserved Set the LCD panel mode and resolution Get the current LCD panel mode, pad strength and resolution Set front porch Get current front porch settings Set the vertical blanking interval between last scan line and next LFRAME pulse Set the vertical blanking interval between last scan line and next LFRAME pulse Set the GPIO configuration. If the GPIO is not used for LCD, set the direction. Otherwise, they are toggled with LCD signals. Get the current GPIO configuration Set GPIO value for GPIO configured as output Read current GPIO status. If the individual GPIO was configured as input, the value is the status of the corresponding pin. Otherwise, it is the programmed value. Set the image post processor Set the image post processor Set the image post processor Set the image post processor Set the rise, fall, period and toggling properties of LCD signal generator 0 Get the current settings of LCD signal generator 0 Set the rise, fall, period and toggling properties of LCD signal generator 1 Get the current settings of LCD signal generator 1 Set the rise, fall, period and toggling properties of LCD signal generator 2 Get the current settings of LCD signal generator 2 Set the rise, fall, period and toggling properties of LCD signal generator 3 Get the current settings of LCD signal generator 3 Set the GPIO0 with respect to the LCD signal generators using ROP operation. No effect if the GPIO0 is configured as general GPIO. Get the GPIO0 properties with respect to the LCD signal generators. Set the GPIO1 with respect to the LCD signal generators using ROP operation. No effect if the GPIO1 is configured as general GPIO. Get the GPIO1 properties with respect to the LCD signal generators. Set the GPIO2 with respect to the LCD signal generators using ROP operation. No effect if the GPIO2 is configured as general GPIO.Solomon SystechMay 2010P 22/94Rev 1.2SSD1963Hex Code 0xCD 0xCE 0xCF 0xD0 0xD1 0xD4 0xD5 0xE0 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xF0 0xF1 0xFFCommand get_gpio2_rop set_gpio3_rop get_gpio3_rop set_dbc_conf get_dbc_conf set_dbc_th get_dbc_th set_pll set_pll_mn get_pll_mn get_pll_status set_deep_sleep set_lshift_freq get_lshift_freq Reserved Reserved set_pixel_data_interface get_pixel_data_interface ReservedDescription Get the GPIO2 properties with respect to the LCD signal generators. Set the GPIO3 with respect to the LCD signal generators using ROP operation. No effect if the GPIO3 is configured as general GPIO. Get the GPIO3 properties with respect to the LCD signal generators. Set the dynamic back light configuration Get the current dynamic back light configuration Set the threshold for each level of power saving Get the threshold for each level of power saving Start the PLL. Before the start, the system was operated with the crystal oscillator or clock input Set the PLL Get the PLL settings Get the current PLL status Set deep sleep mode Set the LSHIFT (pixel clock) frequency Get current LSHIFT (pixel clock) frequency setting Reserved Reserved Set the pixel data format of the parallel host processor interface Get the current pixel data format settings ReservedSSD1963Rev 1.2P 23/94May 2010Solomon Systech9 9.1COMMAND DESCRIPTIONS nop0x00 None D/C 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Hex 00Command ParametersCommand Description No operation.9.2soft_reset0x01 None D/C 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 Hex 01Command ParametersCommandDescription The SSD1963 performs a software reset. All the configuration register will be reset except command 0xE0 to 0xE5. Note : The host processor must wait 5ms before sending any new commands to a SSD1963 following this command.9.3get_power_mode0x0A 1 D/C 0 1 D7 0 0 D6 0 A6 D5 0 A5 D4 0 A4 D3 1 A3 D2 0 A2 D1 1 0 D0 0 0 Hex 0A xxCommand ParametersCommand Parameter 1Description Get the current power mode A[6] : Idle mode on/off (POR = 0) 0 Idle mode off 1 Idle mode on A[5] : Partial mode on/off (POR = 0) 0 Partial mode off 1 Partial mode on A[4] : Sleep mode on/off (POR = 0) 0 Sleep mode on 1 Sleep mode off A[3] : Display normal mode on/off (POR = 1) 0 Display normal mode offSolomon SystechMay 2010P 24/94Rev 1.2SSD19631Display normal mode on (partial mode and vertical scroll off)A[2] : Display on/off (POR = 0) 0 Display is off 1 Display is on9.4get_address_mode0x0B 1 D/C 0 1 D7 0 A7 D6 0 A6 D5 0 A5 D4 0 A4 D3 1 A3 D2 0 A2 D1 1 0 D0 1 0 Hex 0B xxCommand ParametersCommand Parameter 1Description Get the frame buffer to the display panel read order A[7] : Page address order (POR = 0) 0 Top to bottom 1 Bottom to top A[6] : Column address order (POR = 0) 0 Left to right 1 Right to left A[5] : Page / Column order (POR = 0) 0 Normal mode 1 Reverse mode A[4] : Line address order (POR = 0) 0 LCD refresh top to bottom 1 LCD refresh bottom to top A[3] : RGB / BGR order (POR = 0) 0 RGB 1 BGR A[2] : Display data latch data (POR = 0) 0 LCD refresh left to right 1 LCD refresh right to left9.5get_display_mode0x0D 1 D/C 0 1 D7 0 A7 D6 0 0 D5 0 A5 D4 0 0 D3 1 0 D2 1 A2 D1 0 A1 D0 1 A0 Hex 0D xxCommand ParametersCommand Parameter 1Description Get the Display Image Mode status. A[7] : Vertical scrolling on/off (POR = 0) 0 Vertical scrolling is offSSD1963 Rev 1.2 P 25/94 May 2010 Solomon Systech1Vertical scrolling is onA[5] : Invert mode on/off (POR = 0) 0 Inversion is off 1 Inversion is on A[2:0] : Gamma curve selection (POR = 011) 000 Gamma curve 0 001 Gamma curve 1 010 Gamma curve 2 011 Gamma curve 3 100 Reserved 101 Reserved 110 Reserved 111 Reserved9.6get_tear_effect_status0x0E 1 D/C 0 1 D7 0 A7 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 0 D1 1 0 D0 0 0 Hex 0E xxCommand ParametersCommand Parameter 1Description Get the current Tear Effect mode from the SSD1963 A[7] : Tearing effect line mode (POR = 0) 0 Tearing effect off 1 Tearing effect onSolomon SystechMay 2010P 26/94Rev 1.2SSD19639.7enter_sleep_mode0x10 None D/C 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 Hex 10Command ParametersCommandDescription Turn off the panel. This command causes the SSD1963 to enter sleep mode and pull low the GPIO[0] if set_gpio_conf (0xB8) B0 = 0 If GPIO[0] is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf (0xB8), this command will not affect the GPIO[0]. Note : The host processor must wait 5ms before sending any new commands to a SSD1963 following this command.9.8exit_sleep_mode0x11 None D/C 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 Hex 11Command ParametersCommandDescription Turn on the panel. This command causes the SSD1963 to exit sleep mode and will pull high the GPIO[0] if set_gpio_conf (0xB8) B0 = 0. If GPIO[0] is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf (0xB8), this command will not affect the GPIO[0]. Note : The host processor must wait 5ms after sending this command before sending another command. **This command will automatic trigger set_display_on (0x29)9.9enter_partial_mode0x12 None D/C 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 Hex 12Command ParametersCommandDescription Once enter_partial_mode is triggered, the Partial Display Mode window is described by the set_partial_area (0x30). Once enter_normal_mode (0x13) is triggered, partial display mode will end.9.10 enter_normal_modeCommand Parameters 0x13 NoneSSD1963Rev 1.2P 27/94May 2010Solomon SystechCommandD/C 0D7 0D6 0D5 0D4 1D3 0D2 0D1 1D0 1Hex 13Description This command causes the SSD1963 to enter the normal mode. Normal mode is defined as partial display and vertical scroll mode are off. That means the whole display area is used for image display.9.11 exit_invert_modeCommand Parameters 0x20 None D/C 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 Hex 20CommandDescription This command causes the SSD1963 to stop inverting the image data on the display panel. The frame buffer contents remain unchanged. Figure 9-1: Exit Invert mode example Frame Buffer Display Panel?9.12 enter_invert_modeCommand Parameters 0x21 None D/C 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 Hex 21CommandDescription This command causes the SSD1963 to invert the image data only on the display panel. The frame buffer contents remain unchanged.Solomon SystechMay 2010P 28/94Rev 1.2SSD1963Figure 9-2: Enter Invert mode example Frame Buffer Display Panel?9.13 set_gamma_curveCommand Parameters 0x26 1 D/C 0 1 D7 0 0 D6 0 0 D5 1 0 D4 0 0 D3 0 A3 D2 1 A2 D1 1 A1 D0 0 A0 Hex 26 xxCommand Parameter 1Description Selects the gamma curve used by the display panel. A[3:0] 10
Others Gamma curve selection (POR = 1000) No gamma curve selected (Same as 0001b) Gamma curve 0 Gamma curve 1 Gamma curve 2 Gamma curve 3 Reserved GAMAS[1] 0 0 0 1 1 GAMAS[0] 0 0 1 0 19.14 set_display_offCommand Parameters 0x28 None D/C 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 Hex 28CommandDescription Blanks the display panel. The frame buffer contents remain unchanged.9.15 set_display_onCommand Parameters 0x29 None D/C 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1 Hex 29CommandDescription Show the image on the display panelSSD1963Rev 1.2P 29/94May 2010Solomon Systech9.16 set_column_addressCommand Parameters 0x2A 4 D/C 0 1 1 1 1 D7 0 SC15 SC7 EC15 EC7 D6 0 SC14 SC6 EC14 EC6 D5 1 SC13 SC5 EC13 EC5 D4 0 SC12 SC4 EC12 EC4 D3 1 SC11 SC3 EC11 EC3 D2 0 SC10 SC2 EC10 EC2 D1 1 SC9 SC1 EC9 EC1 D0 0 SC8 SC0 EC8 EC0 Hex 2A xx xx xx xxCommand Parameter 1 Parameter 2 Parameter 3 Parameter 4Description Set the column address of frame buffer accessed by the host processor with the read_memory_continue (0x3E) and write_memorty_continue (0x3C).. SC[15:8] : Start column number high byte (POR = ) SC[7:0] : Start column number low byte (POR = ) EC[15:8] : End column number high byte (POR = ) EC[7:0] : End column number low byte (POR = ) Note : SC[15:0] must always be equal to or less than EC[15:0] Figure 9-3: Set Column Address example EC[15:0] D4 0 SP12 SP4 EP12 EP4 D3 1 SP11 SP3 EP11 EP3 SC[15:0]9.17 set_page_addressCommand Parameters 0x2B 4 D/C 0 1 1 1 1 D7 0 SP15 SP7 EP15 EP7 D6 0 SP14 SP6 EP14 EP6 D5 1 SP13 SP5 EP13 EP5 D2 0 SP10 SP2 EP10 EP2 D1 0 SP9 SP1 EP9 EP1 D0 1 SP8 SP0 EP8 EP0 Hex 2B xx xx xx xxCommand Parameter 1 Parameter 2 Parameter 3 Parameter 4Description Set the page address of the frame buffer accessed by the host processor with the read_memory_start (0x2C), write_memory_start (0x2E), read_memory_continue (0x3E) and write_memory_continue (0x3C)..Solomon Systech May 2010 P 30/94 Rev 1.2 SSD1963SP[15:8] : Start page (row) number high byte (POR = ) SP[7:0] : Start page (row) number low byte (POR = ) EP[15:8] : End page (row) number high byte (POR = ) EP[7:0] : End page (row) number low byte (POR = ) Note : SP[15:0] must always be equal to or less than EP[15:0] Figure 9-4: Set Page Address example SP[15:0]EP[15:0]9.18 write_memory_startCommand Parameters 0x2C None D/C 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 0 Hex 2CCommandDescription Transfer image information from the host processor interface to the SSD1963 starting at the location provided by set_column _address (0x2A) and set _page_address (0x2B). If set_address_mdoe (0x36) A[5] = 0: The column and page address are reset to the Start Column (SC) and Start Page (SP), respectively. Pixel Data 1 is stored in frame buffer at (SC, SP). The column address is then incremented and pixels are written to the frame buffer until the column address equals the End Column (EC) value. The column address is then reset to SC and the page address is incremented. Pixels are written to the frame buffer until the page address equals the End Page (EP) value and the column address equals the EC value, or the host processor sends another command. If the number of pixels exceeds (EC C SC + 1) * (EP C SP + 1) the extra pixels are ignored. If set_address_mode (0x36) A[5] = 1: The column and page address are reset to the Start Column (SC) and Start Page (SP), respectively. Pixel Data 1 is stored in frame buffer at (SC, SP). The page address is then incremented and pixels are written to the frame buffer until the page address equals the End Page (EP) value. The page address is then reset to SP and the column address is incremented. Pixels are written to the frame buffer until the column address equals the End column (EC) value and the page address equals the EP value, or the host processor sends another command. If the number of pixels exceeds (EC C SC + 1) * (EP C SP + 1) the extra pixels are ignored.SSD1963Rev 1.2P 31/94May 2010Solomon Systech9.19 read_memory_startCommand Parameters 0x2E None D/C 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 Hex 2ECommandDescription Transfer image data from the SSD1963 to the host processor interface starting at the location provided by set_column_address (0x2A) and set_page_address (0x2B). If set_address_mode A[5] = 0: The column and page address are reset to the Start Column (SC) and Start Page (SP), respectively. Pixels Data 1 are read from frame buffer at (SC, SP). The column address is then incremented and pixels read from the frame buffer until the column address equals the End Column (EC) value. The column address is then reset to SC and the page address is incremented. Pixels are read from the frame buffer until the page address equals the End Page (EP) value and the column address equals the EC value, or the host processor sends another command. If set_address_mode (0x36) A[5] = 1: The column and page address are reset to the Start Column (SC) and Start Page (SP), respectively. Pixels Data 1 are read from frame buffer at (SC, SP). The page address is then incremented and pixels read from the frame buffer until the page address equals the End Page (EP) value. The page address is then reset to SP and the column address is incremented. Pixels are read from the frame buffer until the column address equals the End Column (EC) value and the page address equals the EP value, or the host processor sends another command.9.20 set_partial_areaCommand Parameters 0x30 4 D/C 0 1 1 1 1 D7 0 SR15 SR7 ER15 ER7 D6 0 SR14 SR6 ER14 ER6 D5 1 SR13 SR5 ER13 ER5 D4 1 SR12 SR4 ER12 ER4 D3 0 SR11 SR3 ER11 ER3 D2 0 SR10 SR2 ER10 ER2 D1 0 SR9 SR1 ER9 ER1 D0 0 SR8 SR0 ER8 ER0 Hex 30 xx xx xx xxCommand Parameter 1 Parameter 2 Parameter 3 Parameter 4Description This command defines the Partial Display mode’s display area. There are two parameters associated with this command, the first defines the Start Row (SR) and the second the End Row (ER). SR and ER refer to the Frame Buffer Line Pointer. SR[15:8] : Start display row number high byte (POR = ) SR[7:0] : Start display row number low byte (POR = ) ER[15:8] : End display row number high byte (POR = ) ER[7:0] : End display row number low byte (POR = ) Note : SR[15:0] and ER[15:0] cannot be 0000h nor exceed the last vertical line number.If End Row & Start RowSolomon SystechMay 2010P 32/94Rev 1.2SSD1963Figure 9-5: Set Partial Area with set_address_mode (0x36) A[4] = 0 when End Row & Start RowSR[15:0]Partial AreaER[15:0]Figure 9-6: Set Partial Area with set_address_mode (0x36) A[4] = 1 when End Row & Start RowER[15:0]Partial AreaSR[15:0]If Start Row & End Row Figure 9-7: Set Partial Area with set_address_mode (0x36) A[4] = 0 when Start Row & End Row Partial Area ER[15:0]SR[15:0]Partial AreaFigure 9-8: Set Partial Area with set_address_mode (0x36) A[4] = 1 when Start Row & End RowSSD1963Rev 1.2P 33/94May 2010Solomon SystechPartial Area SR[15:0]ER[15:0] Partial Area9.21 set_scroll_areaCommand Parameters 0x33 6 D/C 0 1 1 1 1 1 1 D7 0 TFA15 TFA7 VSA15 VSA7 BFA15 BFA7 D6 0 TFA14 TFA6 VSA14 VSA6 BFA14 BFA6 D5 1 TFA13 TFA5 VSA13 VSA5 BFA13 BFA5 D4 1 TFA12 TFA4 VSA12 VSA4 BFA12 BFA4 D3 0 TFA11 TFA3 VSA11 VSA3 BFA11 BFA3 D2 0 TFA10 TFA2 VSA10 VSA2 BFA10 BFA2 D1 1 TFA9 TFA1 VSA9 VSA1 BFA9 BFA1 D0 1 TFA8 TFA0 VSA8 VSA0 BFA8 BFA0 Hex 33 xx xx xx xx xx xxCommand Parameter 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6Description Defines the vertical scrolling and fixed area on display area TFA[15:8] : High byte of Top Fixed Area number in lines from the top of the frame buffer (POR = ) TFA[7:0] : Low byte of Top Fixed Area number in lines from the top of the frame buffer (POR = ) VSA[15:8] : High byte of Vertical scrolling area in number of lines of the frame buffer (POR = ) VSA[7:0] : Low byte of Vertical scrolling area in number of lines of the frame buffer (POR = ) BFA[15:8] : High byte of Bottom Fixed Area in number of lines from the bottom of the frame buffer (POR = ) BFA[7:0] : Low byte of Bottom Fixed Area in number of lines from the bottom of the frame buffer (POR = ) If set_address_mode (0x36) A[4] = 0 : The TFA[15:0] describes the Top Fixed Area in number of lines from the top of the frame buffer. The top of the frame buffer and top of the display panel are aligned. The VSA[15:0] describes the height of the Vertical Scrolling Area in number of lines of frame buffer from the Vertical Scrolling Start Address. The first line of the Vertical Scrolling Area starts immediately after the bottom most line of the Top Fixed Area. The last line of the Vertical Scrolling Area ends immediately before the top most line of the Bottom Fixed Area. The BFA[15:0] describes the Bottom Fixed Area in number of lines from the bottom of the frame buffer. The bottom of the frame buffer and bottom of the display panel are aligned. TFA, VSA and BFA refer to the Frame Buffer Line Pointer.Solomon SystechMay 2010P 34/94Rev 1.2SSD1963Figure 9-9: Set Scroll Area with set_address_mode (0x36) A[4] = 0 (0,0) Top Fixed Area TFA[15:0] First line read from memoryVSA[15:0]BFA[15:0] Bottom Fixed AreaIf set_address_mode (0x36) A[4] = 1 : The TFA[15:0], describes the Top Fixed Area in number of lines from the bottom of the frame buffer. The bottom of the frame buffer and bottom of the disp